<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Powerbits | FPGA Firmware &amp; Silicon Security</title><link>https://powerbits.pages.dev/</link><description>Recent content on Powerbits | FPGA Firmware &amp; Silicon Security</description><generator>Hugo -- gohugo.io</generator><language>en</language><managingEditor>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</managingEditor><webMaster>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</webMaster><copyright>© 2026 Mohamed Ihab Eddine ARDJOUNE</copyright><lastBuildDate>Wed, 08 Jul 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://powerbits.pages.dev/index.xml" rel="self" type="application/rss+xml"/><item><title>qmtech-artix-7-workspace: a reproducible build and verification pipeline for the QMTECH Artix-7</title><link>https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/</link><pubDate>Wed, 08 Jul 2026 00:00:00 +0000</pubDate><author>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</author><guid>https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/</guid><description>A containerized Make-driven workspace that takes VHDL/SystemVerilog on a QMTECH Artix-7 from RTL simulation to a JTAG-deployed, SDF-timed bitstream.</description><media:content xmlns:media="http://search.yahoo.com/mrss/" url="https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/feature_pipeline.svg"/></item><item><title>Introduction to FPGAs: Escaping the Tyranny of Fixed Silicon</title><link>https://powerbits.pages.dev/posts/fpga-intro/</link><pubDate>Wed, 01 Jul 2026 12:00:00 +0000</pubDate><author>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</author><guid>https://powerbits.pages.dev/posts/fpga-intro/</guid><description>Field-Programmable Gate Arrays (FPGAs) let you hot-swap physical hardware architectures with code.</description><media:content xmlns:media="http://search.yahoo.com/mrss/" url="https://powerbits.pages.dev/posts/fpga-intro/feature.jpg"/></item><item><title>I'm Ihab</title><link>https://powerbits.pages.dev/about/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><author>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</author><guid>https://powerbits.pages.dev/about/</guid><description>&lt;p&gt;&lt;strong&gt;Mohamed Ihab Eddine ARDJOUNE&lt;/strong&gt; — most people just call me &lt;strong&gt;Ihab&lt;/strong&gt;. You&amp;rsquo;ll also see me written as &lt;strong&gt;M. I. E. ARDJOUNE&lt;/strong&gt; or under my handle &lt;strong&gt;mieardjoune&lt;/strong&gt;. I&amp;rsquo;m an FPGA engineer and ASIC designer based in Algiers, Algeria.&lt;/p&gt;

&lt;h3 class="relative group"&gt;What I Do
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&lt;p&gt;I build secure, high-performance hardware from the ground up:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Cryptography&lt;/strong&gt; – RTL design and implementation of hardware secure cryptographic processors in FPGA / ASIC.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Embedded Drivers and Frameworks&lt;/strong&gt; – Developing low-level drivers and application specific frameworks for FPGAs.&lt;/li&gt;
&lt;/ul&gt;
&lt;blockquote&gt;&lt;p&gt;Want to see the full technical specifications or collaborate on a project? Send me an email at &lt;a href="mailto:ard.iheb@gmail.com" &gt;ard.iheb@gmail.com&lt;/a&gt;.&lt;/p&gt;</description></item></channel></rss>