<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Projects on Powerbits | FPGA Firmware &amp; Silicon Security</title><link>https://powerbits.pages.dev/projects/</link><description>Recent content in Projects on Powerbits | FPGA Firmware &amp; Silicon Security</description><generator>Hugo -- gohugo.io</generator><language>en</language><managingEditor>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</managingEditor><webMaster>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</webMaster><copyright>© 2026 Mohamed Ihab Eddine ARDJOUNE</copyright><lastBuildDate>Wed, 08 Jul 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://powerbits.pages.dev/projects/index.xml" rel="self" type="application/rss+xml"/><item><title>qmtech-artix-7-workspace: a reproducible build and verification pipeline for the QMTECH Artix-7</title><link>https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/</link><pubDate>Wed, 08 Jul 2026 00:00:00 +0000</pubDate><author>ard.iheb@gmail.com (Mohamed Ihab Eddine ARDJOUNE)</author><guid>https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/</guid><description>A containerized Make-driven workspace that takes VHDL/SystemVerilog on a QMTECH Artix-7 from RTL simulation to a JTAG-deployed, SDF-timed bitstream.</description><media:content xmlns:media="http://search.yahoo.com/mrss/" url="https://powerbits.pages.dev/projects/qmtech-artix-7-workspace/feature_pipeline.svg"/></item></channel></rss>